The present invention relates to a technique, effectively applied to a semiconductor integrated circuit device having insulated-gate type field-effect transistors. More particularly this invention relates to a technique effectively applied to a semiconductor integrated circuit device having insulated-gate type field-effect transistors with a thin film structure. This invention also relates to a technique effectively applied to a semiconductor integrated circuit device having static random access memories.
Descriptions concerning the static random access memory are found, for example, in U.S. Pat. No. 4,890,148.
The static random access memory (SRAM: Static Random Access Memory) has one memory cell for one bit formed at an intersection between a complementary data line and a word line. This memory cell comprises a flip-flop circuit as an information storage section and two MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) for data transfer. The flip-flop circuit of the memory cell comprises two drive MOSFETs and two load elements. The load element generally uses either a load MOSFET or a high-resistance load element.
The SRAM of this kind requires at least six elements for each memory cell and thus the occupied area of the memory cell increases, degrading the circuit density. A commonly employed technique for reducing the occupied area of the memory cell is to arrange the load elements in a layer over the drive MOSFETs of the memory cell so that they overlap the drive MOSFETs. This technique forms elements: in a polycrystalline silicon film deposited over the principal plane of the monocrystal silicon substrate and is generally called an SOI (Silicon On Insulator) technique. This technique is also called a TFT (Thin Film Transistor) technique when the load MOSFETs are formed as the load elements.
However, even with the SOI technique or the TFT technique, one memory cell requires a total of four elements--two transfer MOSFETs and two drive MOSFETs--to be formed on a principal plane of the monocrystalline silicon substrate. That is, the memory cell fails to reduce its occupied area and therefore these techniques cannot be expected to make significant contributions to higher circuit density of SRAM.